Mainly, so-termed chip scale packages (CSPs) are concerned here. These are in fact not packages with a separate package carrier and an encapsulation, but semiconductor components with a stress relief structure on top of the passivation layer. A semiconductor substrate, e.g. comprising an electrical element like a diode, a transistor, a MEMS (Micro-Electro-Mechanical Element) or a capacitor, is fixed to a board, such as a printed circuit board (PCB), by means of solder balls without using an additional carrier. A CSP is used inter alia for so-termed power transistors and for electrostatic discharge (ESD) diodes, usually in combination with a passive filter comprising resistors, capacitors and/or coils. CSPs are furthermore used in particular for electric circuits with a limited number of I/Os for applications where size is relevant. An example hereof is an audio circuit for a frequency modulation (FM) radio. This is a semiconductor with an amplifier and a tuner and any circuits that may further be required, which is capable of performing a radio function in a mobile telephone in its entirety. Partially because of the small amount of space that is available in a mobile telephone, the size of the package is of the essence in this case.
Generally, the solder balls of a CSP are mounted directly on a motherboard or PCB provided with electrodes corresponding to the solder balls. The solder balls are soldered onto the board to obtain an electronic device. During said soldering and during use of the device, stresses will occur as a result of the differences in thermal expansion between the material of the board and, for example, the silicon of a semiconductor. Said stresses occur in particular in the solder balls and at the interface of the solder balls and the underlying structure. If no measures are taken, this will lead to an insufficient degree of reliability of the electronic device, in particular during thermal cycling (TMCL) and fall tests. This has led to the provision of stress buffering packages as described in the following paragraphs, in which a stress buffering means for absorbing stresses is provided between the I/O pads and the solder balls.
US patent document US2004/0082101 discusses a CSP that makes use of an insulating stress absorbing resin layer. The associated package 10 is shown in FIG. 1. The stress absorbing resin layer 12, which is made of a thermosetting resin such as epoxy resin or polyimide resin, has a modulus of elasticity of 0.01-8 Gpa and is relatively flexible, therefore. After the resin layer has been coated on the passivation layer 14, holes are etched so as to expose the so-termed I/O pads. Then the holes are filled with a flexible conductive layer 18. The conductive layer comprises a powdery material of at least one of copper, lead, tin, nickel, palladium, silver or gold. Finally, solder balls 20 are placed on the conductive layer 18. The stress absorbing layer 12 and the conductive layer 18 jointly form a stress buffering means 22. The layer 12 is made of an elastic material having a thermal expansion coefficient of 40-600 ppm/K. For all the embodiments that are shown in US2004/0082101 it obtains that the stress buffering means 22 is uninterrupted, at least from a thermomechanical point of view. Because both the stress absorbing layer 12 and the conductive layer 18 are flexible, stress occurring in one of the solder balls can be transmitted to adjacent solder balls via the stress buffering means 22.
The method as discussed in US2004/0082101 comprises a number of difficult and costly steps such as lithography, etching, plasma surface treatments, screen printing, etc. In addition, the conductive layer 18 comprises materials which present problems when manufacturing semiconductors, in particular in the waferfab. The use of materials such as copper or gold may lead to the electronic circuits in the silicon being affected.
Another known solution is presented in FIG. 2, which shows a package 30 in which a stress absorbing layer 32 of polyimide is provided on top of a passivation layer 34. An opening is present in the layer 32, which opening at least partially coincides, seen in projection, with the opening in the passivation layer. An underbump metallization (UBM) 36 is present partially on the stress absorbing layer 32 and partially in the opening (for contact with the I/O pads 40). The UBM thus has the shape of an upside-down cowboy hat. The UBM does not fill the openings in the passivation layer and the buffer layer completely, so that a hollow is formed. As a result, the solder balls 38 are partially present in said hollow. In this solution, too, a stress buffering means comprising the stress absorbing layer 32 and the UBM layers is thermomechanically uninterrupted. The fact of the matter is that the UBM layer is a hard layer, certainly in comparison with the material of the stress absorbing layer and the solder balls, which hard layer generally comprises nickel and which will transmit the stresses that occur to the adjacent UBM structures via the surrounding polyimide layer.
Varying phases of heating and cooling occur during TMCL. This is discussed, for example, in patent documents GB 2,135,525 and EP 0 064 854. It is also known for ball grid array (BGA) packages. It is a generally known fact that the largest problems with TMCL normally occur at the solder balls furthest away from the center of the package (i.e. the center of the semiconductor, also referred to as the neutral point). After all, in TMCL the board expands more than the semiconductor. The left-hand edge of the semiconductor is pulled to the left and the right-hand edge is pulled to the right relative to the center of the semiconductor upon heating, therefore. The difference in movement between the semiconductor and the board is much larger at the edge of the semiconductor than somewhere in the center.